{"id":4401,"date":"2025-06-07T22:37:54","date_gmt":"2025-06-07T15:37:54","guid":{"rendered":"https:\/\/labantrithuc.com\/?p=4401"},"modified":"2025-06-07T22:40:59","modified_gmt":"2025-06-07T15:40:59","slug":"quy-trinh-thiet-ke-ip-28-nm-non-fab","status":"publish","type":"post","link":"https:\/\/labantrithuc.com\/?p=4401","title":{"rendered":"Quy Tr\u00ecnh Thi\u1ebft K\u1ebf IP 28 nm Non-Fab"},"content":{"rendered":"\n<figure class=\"wp-block-audio\"><audio controls src=\"https:\/\/labantrithuc.com\/wp-content\/uploads\/2025\/06\/Quy-Trinh-Thiet-Ke-IP-28-nm-Non-Fab.wav\" autoplay><\/audio><\/figure>\n\n\n\n<p>Trong ng\u00e0nh b\u00e1n d\u1eabn hi\u1ec7n \u0111\u1ea1i, vi\u1ec7c ph\u00e1t tri\u1ec3n m\u1ed9t IP (Intellectual Property) \u2014 ch\u1eb3ng h\u1ea1n nh\u01b0 m\u1ed9t b\u1ed9 nh\u00e2n (Multiplier), FIFO hay b\u1ed9 l\u1ecdc FIR \u2014 tr\u00ean ti\u1ebfn tr\u00ecnh c\u00f4ng ngh\u1ec7 28 nm \u0111\u00f2i h\u1ecfi m\u1ed9t quy tr\u00ecnh to\u00e0n di\u1ec7n, ch\u00ednh x\u00e1c v\u00e0 tu\u00e2n th\u1ee7 ti\u00eau chu\u1ea9n qu\u1ed1c t\u1ebf. Tuy nhi\u00ean, kh\u00f4ng ph\u1ea3i t\u1ed5 ch\u1ee9c n\u00e0o c\u0169ng s\u1edf h\u1eefu x\u01b0\u1edfng s\u1ea3n xu\u1ea5t (fab) ri\u00eang. M\u00f4 h\u00ecnh \u201cnon-fab\u201d (hay c\u00f2n g\u1ecdi l\u00e0 \u201cDesign-Only\u201d) \u0111\u00e3 tr\u1edf th\u00e0nh xu h\u01b0\u1edbng ph\u1ed5 bi\u1ebfn, trong \u0111\u00f3 c\u00e1c nh\u00f3m thi\u1ebft k\u1ebf ho\u00e0n thi\u1ec7n to\u00e0n b\u1ed9 chu\u1ed7i t\u1eeb RTL (Register-Transfer Level) \u0111\u1ebfn GDSII v\u00e0 k\u00fd \u201ctape-out\u201d th\u00f4ng qua d\u1ecbch v\u1ee5 Multi-Project Wafer (MPW) c\u1ee7a c\u00e1c nh\u00e0 m\u00e1y \u0111\u00fac (foundry) ho\u1eb7c c\u00e1c ch\u01b0\u01a1ng tr\u00ecnh shuttle (nh\u01b0 TSMC Shuttle Program, MOSIS). B\u00e0i vi\u1ebft n\u00e0y s\u1ebd gi\u1edbi thi\u1ec7u t\u00f3m t\u1eaft quy tr\u00ecnh thi\u1ebft k\u1ebf IP 28 nm non-fab, h\u01b0\u1edbng t\u1edbi \u0111\u00e0o t\u1ea1o v\u00e0 th\u1ef1c h\u00e0nh cho sinh vi\u00ean k\u1ef9 thu\u1eadt ho\u1eb7c c\u00e1c k\u1ef9 s\u01b0 chuy\u1ec3n \u0111\u1ed5i sang l\u0129nh v\u1ef1c thi\u1ebft k\u1ebf vi m\u1ea1ch.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"568\" src=\"https:\/\/labantrithuc.com\/wp-content\/uploads\/2025\/06\/NotebookLM-Mind-Map-1024x568.png\" alt=\"\" class=\"wp-image-4403\" srcset=\"https:\/\/labantrithuc.com\/wp-content\/uploads\/2025\/06\/NotebookLM-Mind-Map-1024x568.png 1024w, https:\/\/labantrithuc.com\/wp-content\/uploads\/2025\/06\/NotebookLM-Mind-Map-300x166.png 300w, https:\/\/labantrithuc.com\/wp-content\/uploads\/2025\/06\/NotebookLM-Mind-Map-768x426.png 768w, https:\/\/labantrithuc.com\/wp-content\/uploads\/2025\/06\/NotebookLM-Mind-Map-1536x852.png 1536w, https:\/\/labantrithuc.com\/wp-content\/uploads\/2025\/06\/NotebookLM-Mind-Map-2048x1136.png 2048w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<p><strong>1. \u0110\u1ecbnh ngh\u0129a y\u00eau c\u1ea7u (Specification)<\/strong><br>Quy tr\u00ecnh b\u1eaft \u0111\u1ea7u b\u1eb1ng vi\u1ec7c x\u00e1c \u0111\u1ecbnh r\u00f5 <strong>URS (User Requirements Specification)<\/strong>: m\u00f4 t\u1ea3 ch\u1ee9c n\u0103ng ch\u00ednh c\u1ee7a IP, th\u00f4ng s\u1ed1 k\u1ef9 thu\u1eadt (v\u00ed d\u1ee5 \u0111\u1ed9 r\u1ed9ng d\u1eef li\u1ec7u, t\u1ea7n s\u1ed1 m\u1ee5c ti\u00eau), y\u00eau c\u1ea7u v\u1ec1 n\u0103ng l\u01b0\u1ee3ng, \u0111i\u1ec7n \u00e1p cung c\u1ea5p (VDD = 0,9 V; VSS = 0 V) v\u00e0 d\u1ea3i nhi\u1ec7t \u0111\u1ed9 ho\u1ea1t \u0111\u1ed9ng (\u221240 \u00b0C \u2026 +85 \u00b0C). V\u1edbi b\u1ed9 nh\u00e2n 16\u00d716 bit, c\u1ea7n x\u00e1c \u0111\u1ecbnh ki\u1ebfn tr\u00fac (Wallace-Tree, Booth hay shift-add), t\u1ea7n s\u1ed1 \u2265 1 GHz v\u00e0 c\u00f4ng su\u1ea5t \u2264 10 mW. V\u1edbi FIFO, x\u00e1c \u0111\u1ecbnh s\u00e2u 1024 \u00d7 32 bit, \u0111\u1ecdc-ghi \u0111\u1ed3ng th\u1eddi \u1edf 500 MHz v\u00e0 c\u00e1c t\u00edn hi\u1ec7u empty\/full. V\u1edbi b\u1ed9 l\u1ecdc FIR, c\u1ea7n t\u00ednh to\u00e1n s\u1ed1 tap = 16, \u0111\u1ed9 r\u1ed9ng fixed-point 12\u201316 bit, sampling rate 200 MHz v\u00e0 SNR \u2265 60 dB. \u0110\u1ed3ng th\u1eddi, giao di\u1ec7n I\/O (data_in[N\u20131:0], data_out[M\u20131:0], clock, reset, valid\/ready) v\u00e0 c\u00e1c r\u00e0ng bu\u1ed9c timing (setup-hold, max input\/output delay) ph\u1ea3i \u0111\u01b0\u1ee3c li\u1ec7t k\u00ea chi ti\u1ebft trong URS.<\/p>\n\n\n\n<p><strong>2. Thi\u1ebft k\u1ebf RTL (Register-Transfer Level)<\/strong><br>T\u1eeb URS, nh\u00f3m thi\u1ebft k\u1ebf l\u1ef1a ch\u1ecdn ki\u1ebfn tr\u00fac ph\u00f9 h\u1ee3p: v\u00ed d\u1ee5 \u201cWallace-Booth\u201d \u0111\u1ec3 t\u1ed1i \u01b0u \u0111\u1ed9 tr\u1ec5 ho\u1eb7c \u201carray multiplier\u201d \u0111\u1ec3 ti\u1ebft ki\u1ec7m di\u1ec7n t\u00edch. Trong tr\u01b0\u1eddng h\u1ee3p FIFO, n\u1ebfu \u0111\u1ed9 s\u00e2u l\u1edbn, s\u1eed d\u1ee5ng Block RAM dual-port; n\u1ebfu s\u00e2u nh\u1ecf, c\u00f3 th\u1ec3 d\u00f9ng shift-register. V\u1edbi FIR, c\u00e2n nh\u1eafc gi\u1eefa thi\u1ebft k\u1ebf fully parallel (t\u0103ng throughput) ho\u1eb7c semi-parallel (ti\u1ebft ki\u1ec7m t\u00e0i nguy\u00ean). Ti\u1ebfp theo, m\u00f4 t\u1ea3 h\u00e0nh vi (behavioral) v\u00e0 c\u1ea5u tr\u00fac (structural) c\u1ee7a IP b\u1eb1ng Verilog\/SystemVerilog ho\u1eb7c VHDL, s\u1eed d\u1ee5ng parameter (nh\u01b0 WIDTH, DEPTH) \u0111\u1ec3 t\u00e1i s\u1eed d\u1ee5ng. N\u1ebfu y\u00eau c\u1ea7u t\u1ea7n s\u1ed1 cao (\u2265 1 GHz), nh\u00f3m thi\u1ebft k\u1ebf th\u00eam pipelining, ph\u00e2n chia th\u00e0nh nhi\u1ec1u stage v\u00e0 ch\u00e8n register gi\u1eefa c\u00e1c stage \u0111\u1ec3 \u0111\u1ea3m b\u1ea3o m\u1ed7i stage c\u00f3 delay \u2264 200 \u2013 300 ps. Cu\u1ed1i c\u00f9ng, vi\u1ebft testbench RTL bao g\u1ed3m directed test vectors v\u00e0 random stimulus, ch\u1ea1y m\u00f4 ph\u1ecfng ch\u1ee9c n\u0103ng (ModelSim, QuestaSim ho\u1eb7c VCS) \u0111\u1ec3 ki\u1ec3m tra corner cases (reset, sign-extension, overflow, clock domain crossing) v\u00e0 b\u00e1o c\u00e1o coverage (SystemVerilog Assertions).<\/p>\n\n\n\n<p><strong>3. T\u1ed5ng h\u1ee3p (Synthesis)<\/strong><br>Sau khi RTL \u0111\u00e3 ho\u00e0n ch\u1ec9nh v\u1ec1 m\u1eb7t ch\u1ee9c n\u0103ng, b\u01b0\u1edbc ti\u1ebfp theo l\u00e0 <strong>synthesis<\/strong>: chuy\u1ec3n RTL sang gate-level netlist. Nh\u00f3m thi\u1ebft k\u1ebf chu\u1ea9n b\u1ecb PDK 28 nm (TSMC OOC 28 nm educational PDK ch\u1ee9a file LEF, Liberty (.lib) v\u00e0 tech lef). S\u1eed d\u1ee5ng c\u00f4ng c\u1ee5 Synopsys Design Compiler ho\u1eb7c Cadence Genus, thi\u1ebft l\u1eadp project v\u1edbi c\u00e1c constraint (.sdc): create_clock \u2013period 1.0 ns, set_input_delay 0.1 ns, set_output_delay 0.1 ns, set_max_transition 0.2 ns, set_max_fanout 10. Ch\u1ea1y compile_ultra \u2013gate_clock \u0111\u1ec3 t\u1ea1o netlist v\u00e0 xu\u1ea5t file .sdf. Sau \u0111\u00f3, nh\u00f3m ki\u1ec3m tra timing report (WNS \u2265 0, TNS \u2265 0), area report (t\u1ed5ng cell count, t\u1ed5ng di\u1ec7n t\u00edch), power report (dynamic, leakage, short-circuit). \u0110\u1ed3ng th\u1eddi, ch\u1ea1y linting (SpyGlass ho\u1eb7c Jasper) \u0111\u1ec3 ph\u00e1t hi\u1ec7n coding style violations, reset domain issues, ho\u1eb7c clock domain crossing, tr\u01b0\u1edbc khi chuy\u1ec3n sang physical design.<\/p>\n\n\n\n<p><strong>4. Thi\u1ebft k\u1ebf v\u1eadt l\u00fd (Physical Design)<\/strong><br>B\u01b0\u1edbc physical design bao g\u1ed3m floorplanning, placement, clock tree synthesis (CTS) v\u00e0 routing. Trong floorplanning, x\u00e1c \u0111\u1ecbnh die-outline d\u1ef1a tr\u00ean area report t\u1eeb synthesis \u2014 v\u00ed d\u1ee5 t\u1ed5ng cell area \u2248 0,02 mm\u00b2 \u21d2 die size ~200 \u00b5m \u00d7 200 \u00b5m (g\u1ed3m margin routing). \u0110\u1eb7t power rails (VDD\/VSS) v\u1edbi spacing h\u1ee3p l\u1ec7 v\u00e0 x\u00e1c \u0111\u1ecbnh khu v\u1ef1c blockages (nh\u01b0 d\u00e0nh cho PLL ho\u1eb7c analog). Ti\u1ebfp theo, ch\u1ea1y placement (max_utilization = 75 %) \u0111\u1ec3 gi\u1ea3m congestion (&lt; 70 %) v\u00e0 HPWL. Sau \u0111\u00f3, th\u1ef1c hi\u1ec7n CTS v\u1edbi skew \u2264 50 ps, insertion delay \u2264 100 ps, ch\u00e8n buffer clock v\u00e0 routing clock tree (M2\u2013M4). Trong routing, nh\u00f3m th\u1ef1c hi\u1ec7n global routing, t\u1ea1o congestion map, r\u1ed3i detail routing theo lu\u1eadt DRC (minimum width\/spacing, via enclosure, s\u1eed d\u1ee5ng metal layers M1\u2013M9, via rules V1\u2013V8), \u0111\u1ed3ng th\u1eddi xu\u1ea5t DRC v\u00e0 LVS reports s\u01a1 b\u1ed9 r\u1ed3i fix cho \u0111\u1ebfn khi kh\u00f4ng c\u00f2n l\u1ed7i.<\/p>\n\n\n\n<p><strong>5. Ph\u00e2n t\u00edch v\u00e0 ki\u1ec3m th\u1eed (Sign-off)<\/strong><br>Sau khi PnR ho\u00e0n t\u1ea5t, nh\u00f3m ch\u1ea1y STA (Static Timing Analysis) b\u1eb1ng PrimeTime ho\u1eb7c Tempus, ki\u1ec3m tra WNS \u2265 0 v\u00e0 TNS \u2265 0 cho c\u00e1c corner TT (Typical), SS (Slow-Slow), FF (Fast-Fast). N\u1ebfu c\u00f3 violation, c\u1ea7n t\u1ed1i \u01b0u buffer insertion, restructure logic ho\u1eb7c \u0111i\u1ec1u ch\u1ec9nh clock tree. Ti\u1ebfp \u0111\u00f3, ch\u1ea1y power analysis: import switching activity file (.vcd ho\u1eb7c .saif) t\u1eeb simulation, s\u1eed d\u1ee5ng PrimePower ho\u1eb7c Voltus \u0111\u1ec3 t\u00ednh dynamic power; t\u00ednh leakage power d\u1ef1a tr\u00ean .lib \u1edf corner T = 85 \u00b0C, VDD = 0,9 V; r\u1ed3i t\u1ed5ng h\u1ee3p v\u00e0 ki\u1ec3m tra t\u1ed5ng power ph\u1ea3i \u2264 target (v\u00ed d\u1ee5 \u2264 10 mW). N\u1ebfu v\u01b0\u1ee3t, nh\u00f3m ti\u1ebfn h\u00e0nh t\u1ed1i \u01b0u multi-Vt cells, clock gating, power gating. \u0110\u1ed1i v\u1edbi DRC &amp; LVS sign-off, s\u1eed d\u1ee5ng Cadence Pegasus ho\u1eb7c Mentor Calibre \u0111\u1ec3 \u0111\u1ea3m b\u1ea3o 0 l\u1ed7i DRC v\u00e0 layout vs schematic match. N\u1ebfu PDK y\u00eau c\u1ea7u, nh\u00f3m th\u1ef1c hi\u1ec7n Arduino Check (antenna) v\u00e0 fix. Trong tr\u01b0\u1eddng h\u1ee3p foundry \u0111\u00f2i h\u1ecfi parasitic extraction (PEX), nh\u00f3m ch\u1ea1y StarRC (Synopsys) ho\u1eb7c Mentor Fx \u0111\u1ec3 tr\u00edch xu\u1ea5t parasitic RC, sau \u0111\u00f3 ch\u1ea1y STA l\u1ea1i v\u1edbi file .spf ho\u1eb7c .spef \u0111\u1ec3 \u0111\u1ea3m b\u1ea3o timing closure.<\/p>\n\n\n\n<p><strong>6. Xu\u1ea5t GDSII v\u00e0 t\u00e0i li\u1ec7u<\/strong><br>Khi m\u1ecdi sign-off criteria (DRC, LVS, STA post-PEX, power) \u0111\u1ec1u \u0111\u1ea1t, nh\u00f3m th\u1ef1c hi\u1ec7n xu\u1ea5t GDSII: l\u1ef1a ch\u1ecdn hierarchical GDSII ho\u1eb7c flattened GDSII theo y\u00eau c\u1ea7u foundry (v\u00ed d\u1ee5 TSMC 28 nm GDS rules). \u0110\u1ed3ng th\u1eddi t\u1ea1o t\u00e0i li\u1ec7u \u0111i k\u00e8m g\u1ed3m Schematic PDF (block diagram &amp; detailed schematic), LEF file (abstract view), Liberty .lib (abstract cell), constraint file .sdc, v\u00e0 m\u1ed9t README chi ti\u1ebft g\u1ed3m th\u00f4ng tin PPA summary (peak frequency, total power, total area), pin assignment, timing arcs, power rails, h\u01b0\u1edbng d\u1eabn integrate IP v\u00e0o SoC (ch\u1ea1y synthesis\/P&amp;R l\u1ea1i khi thay \u0111\u1ed5i clock, generate Liberty abstract cell) v\u00e0 license statement n\u1ebfu IP c\u00f3 cell proprietary. Cu\u1ed1i c\u00f9ng, nh\u00f3m chu\u1ea9n b\u1ecb tape-out checklist: DRC sign-off report, LVS sign-off report, STA sign-off report (post-PEX), ERC (Electrical Rule Check) \u0111\u1ec3 \u0111\u1ea3m b\u1ea3o pin connections v\u00e0 voltage domains h\u1ee3p l\u1ec7, r\u1ed3i package GDSII v\u00e0 doc package g\u1eedi foundry (TSMC, Intel ho\u1eb7c Samsung).<\/p>\n\n\n\n<p><strong>7. M\u00f4i tr\u01b0\u1eddng non-fab v\u00e0 c\u00f4ng c\u1ee5 h\u1ed7 tr\u1ee3<\/strong><br>Trong m\u00f4 h\u00ecnh non-fab, nh\u00f3m thi\u1ebft k\u1ebf t\u1eadn d\u1ee5ng d\u1ecbch v\u1ee5 MPW (TSMC Shuttle Program, MOSIS) \u0111\u1ec3 gi\u1ea3m chi ph\u00ed s\u1ea3n xu\u1ea5t th\u1eed. Ngo\u00e0i ra, nh\u00f3m x\u00e2y d\u1ef1ng m\u00f4i tr\u01b0\u1eddng Cloud-Based EDA (HPC) b\u1eb1ng c\u00e1ch t\u1ea1o Docker container ch\u1ee9a license Cadence, Synopsys, Mentor (Design Compiler, PrimeTime, Innovus, Calibre) v\u00e0 s\u1eed d\u1ee5ng AWS EC2 HPC, FPT CMC Cloud ho\u1eb7c Viettel IDC \u0111\u1ec3 ch\u1ea1y c\u00e1c job synthesis, P&amp;R v\u00e0 sign-off song song, gi\u1ea3m turnaround time. N\u1ebfu kh\u00f4ng c\u00f3 PDK 28 nm, nh\u00f3m c\u0169ng c\u00f3 th\u1ec3 th\u1ef1c h\u00e0nh quy tr\u00ecnh c\u00f4ng vi\u1ec7c b\u1eb1ng Open-Source Flow (OpenROAD\/OpenLane) v\u1edbi PDK c\u00f4ng khai SkyWater 130 nm, gi\u00fap sinh vi\u00ean n\u1eafm v\u1eefng c\u00e1c b\u01b0\u1edbc floorplan, placement, CTS, routing v\u00e0 sign-off. Ngo\u00e0i ra, ph\u00f2ng lab \u1ea3o (VM ho\u1eb7c Docker image) v\u1edbi OpenROAD, Magic, Qflow \u0111\u01b0\u1ee3c tri\u1ec3n khai \u0111\u1ec3 sinh vi\u00ean k\u1ebft n\u1ed1i SSH \u0111\u1ebfn HPC\/Cluster v\u00e0 th\u1ef1c h\u00e0nh tr\u1ef1c ti\u1ebfp.<\/p>\n\n\n\n<p><strong>8. T\u1ed1i \u01b0u PPA v\u00e0 Multi-Corner Analysis<\/strong><br>Qu\u00e1 tr\u00ecnh t\u1ed1i \u01b0u PPA (Power\/Performance\/Area) l\u00e0 b\u01b0\u1edbc then ch\u1ed1t sau khi \u0111\u00e3 c\u00f3 layout ban \u0111\u1ea7u. Nh\u00f3m ti\u1ebfn h\u00e0nh t\u1ed1i \u01b0u <strong>area<\/strong> b\u1eb1ng c\u00e1ch s\u1eed d\u1ee5ng standard cells M0\/M1 (thin gate) \u1edf nh\u1eefng v\u00f9ng kh\u00f4ng critical; <strong>reduce power<\/strong> qua clock gating, multi-Vt cells v\u00e0 power gating cho c\u00e1c sub-blocks idle; <strong>n\u00e2ng cao performance<\/strong> b\u1eb1ng c\u00e1ch t\u0103ng pipeline depth, restructure combinational logic, th\u00eam buffers t\u1ea1i fan-out cao. B\u00ean c\u1ea1nh \u0111\u00f3, nh\u00f3m th\u1ef1c hi\u1ec7n Multi-Corner Multi-Mode (MCMM) analysis: ch\u1ea1y STA cho TT, SS, FF, TT+SS, TT+FF v\u00e0 c\u00e1c ch\u1ebf \u0111\u1ed9 ho\u1ea1t \u0111\u1ed9ng (normal, test, sleep). N\u1ebfu ph\u00e1t hi\u1ec7n timing violations, ph\u1ea3i \u0111i\u1ec1u ch\u1ec9nh l\u1ea1i buffer insertion, cell sizing ho\u1eb7c clock tree insertion. \u0110\u1ed3ng th\u1eddi, ti\u1ebfn h\u00e0nh <strong>EM\/IR Drop Analysis<\/strong> (Voltus EMI ho\u1eb7c RedHawk) \u0111\u1ec3 ki\u1ec3m tra IR drop \u2264 5 % VDD, tr\u00e1nh hotspot. Cu\u1ed1i c\u00f9ng, <strong>Aging Analysis<\/strong> (BTI, HCI) b\u1eb1ng PrimeTime SI ho\u1eb7c t\u01b0\u01a1ng \u0111\u01b0\u01a1ng \u0111\u1ec3 x\u00e1c \u0111\u1ecbnh s\u1ee9c b\u1ec1n (reliability) c\u1ee7a IP; n\u1ebfu c\u00f3 violation, th\u00eam margin timing ho\u1eb7c \u0111\u1ec1 xu\u1ea5t gi\u1ea3i ph\u00e1p adaptive body biasing.<\/p>\n\n\n\n<p><strong>9. K\u1ebft qu\u1ea3 \u0111\u1ea7u ra (Deliverables)<\/strong><br>K\u1ebft th\u00fac quy tr\u00ecnh, nh\u00f3m thi\u1ebft k\u1ebf b\u00e0n giao tr\u1ecdn b\u1ed9 deliverables:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>RTL &amp; Testbench<\/strong>: m\u00e3 Verilog\/SystemVerilog, testbench RTL, constraint .sdc v\u00e0 b\u00e1o c\u00e1o m\u00f4 ph\u1ecfng (waveform, coverage, SVA assertions).<\/li>\n\n\n\n<li><strong>Synthesized Netlist<\/strong>: gate-level netlist (.v), SDF (.sdf) v\u00e0 b\u00e1o c\u00e1o synthesis (timing, area, power).<\/li>\n\n\n\n<li><strong>Physical Design Database &amp; Reports<\/strong>: th\u01b0 m\u1ee5c Innovus\/ICC2 project (netlist, .lef, .def, .mag, routing DB) c\u00f9ng c\u00e1c b\u00e1o c\u00e1o placement utilization, congestion map, clock tree report, timing sign-off.<\/li>\n\n\n\n<li><strong>Sign-off Reports<\/strong>: DRC sign-off, LVS sign-off, STA sign-off (post-PEX) v\u00e0 power sign-off, k\u00e8m Antenna Check (n\u1ebfu y\u00eau c\u1ea7u).<\/li>\n\n\n\n<li><strong>GDSII &amp; Documentation Package<\/strong>: file GDSII (.gds hierarchical ho\u1eb7c flattened) c\u00f9ng t\u00e0i li\u1ec7u k\u00e8m (schematic PDF, LEF, Liberty .lib, README tr\u00ecnh b\u00e0y PPA summary, pin assignment, integration notes, license statement).<\/li>\n\n\n\n<li><strong>Integration Notes<\/strong>: h\u01b0\u1edbng d\u1eabn c\u00e1ch t\u00edch h\u1ee3p IP v\u00e0o SoC (ch\u1ea1y synthesis\/P&amp;R l\u1ea1i khi thay \u0111\u1ed5i clock, generate Liberty abstract cell, t\u1ea1o stub macros, thi\u1ebft l\u1eadp testbench c\u1ea5p SoC \u0111\u1ec3 verify), c\u00e1ch t\u00e1i-characterize \u1edf c\u00e1c corner SS\/FF v\u00e0 c\u00e1ch t\u1ea1o pin wrappers.<\/li>\n<\/ul>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n\n\n\n<p>T\u00f3m l\u1ea1i, quy tr\u00ecnh thi\u1ebft k\u1ebf m\u1ed9t IP 28 nm trong m\u00f4i tr\u01b0\u1eddng non-fab bao g\u1ed3m ch\u00edn b\u01b0\u1edbc ch\u00ednh: \u0111\u1ecbnh ngh\u0129a y\u00eau c\u1ea7u, thi\u1ebft k\u1ebf RTL, synthesis, physical design, sign-off, xu\u1ea5t GDSII, s\u1eed d\u1ee5ng m\u00f4i tr\u01b0\u1eddng non-fab, t\u1ed1i \u01b0u PPA v\u00e0 b\u00e0n giao deliverables. M\u1ed7i b\u01b0\u1edbc \u0111\u1ec1u bao g\u1ed3m c\u00e1c c\u00f4ng vi\u1ec7c chi ti\u1ebft, t\u1eeb thi\u1ebft l\u1eadp \u0111i\u1ec1u ki\u1ec7n ban \u0111\u1ea7u \u0111\u1ebfn k\u1ebft qu\u1ea3 cu\u1ed1i c\u00f9ng s\u1eb5n s\u00e0ng g\u1eedi foundry tape-out. M\u00f4 h\u00ecnh \u201cDesign-Only\u201d kh\u00f4ng y\u00eau c\u1ea7u s\u1edf h\u1eefu x\u01b0\u1edfng s\u1ea3n xu\u1ea5t, gi\u00fap c\u00e1c t\u1ed5 ch\u1ee9c, ph\u00f2ng \u0111\u00e0o t\u1ea1o v\u00e0 sinh vi\u00ean th\u1ef1c h\u00e0nh \u0111\u1ea7y \u0111\u1ee7 quy tr\u00ecnh thi\u1ebft k\u1ebf vi m\u1ea1ch theo ti\u00eau chu\u1ea9n qu\u1ed1c t\u1ebf, \u0111\u1ed3ng th\u1eddi gi\u1ea3m thi\u1ec3u chi ph\u00ed s\u1ea3n xu\u1ea5t th\u1eed nghi\u1ec7m v\u00e0 t\u0103ng c\u01a1 h\u1ed9i ti\u1ebfp c\u1eadn c\u00f4ng ngh\u1ec7 ti\u00ean ti\u1ebfn.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Trong ng\u00e0nh b\u00e1n d\u1eabn hi\u1ec7n \u0111\u1ea1i, vi\u1ec7c ph\u00e1t tri\u1ec3n m\u1ed9t IP (Intellectual Property) \u2014 ch\u1eb3ng h\u1ea1n nh\u01b0 m\u1ed9t b\u1ed9 nh\u00e2n (Multiplier), FIFO hay b\u1ed9 l\u1ecdc FIR \u2014 tr\u00ean ti\u1ebfn tr\u00ecnh c\u00f4ng ngh\u1ec7 28 nm \u0111\u00f2i h\u1ecfi m\u1ed9t quy tr\u00ecnh to\u00e0n di\u1ec7n, ch\u00ednh x\u00e1c v\u00e0 tu\u00e2n th\u1ee7 ti\u00eau chu\u1ea9n qu\u1ed1c t\u1ebf. Tuy nhi\u00ean, kh\u00f4ng ph\u1ea3i t\u1ed5&#8230;<\/p>\n","protected":false},"author":1,"featured_media":4403,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_kadence_starter_templates_imported_post":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[3],"tags":[50],"class_list":["post-4401","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-cong-nghe","tag-thiet-ke-vi-mach"],"_links":{"self":[{"href":"https:\/\/labantrithuc.com\/index.php?rest_route=\/wp\/v2\/posts\/4401","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/labantrithuc.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/labantrithuc.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/labantrithuc.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/labantrithuc.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=4401"}],"version-history":[{"count":2,"href":"https:\/\/labantrithuc.com\/index.php?rest_route=\/wp\/v2\/posts\/4401\/revisions"}],"predecessor-version":[{"id":4405,"href":"https:\/\/labantrithuc.com\/index.php?rest_route=\/wp\/v2\/posts\/4401\/revisions\/4405"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/labantrithuc.com\/index.php?rest_route=\/wp\/v2\/media\/4403"}],"wp:attachment":[{"href":"https:\/\/labantrithuc.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=4401"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/labantrithuc.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=4401"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/labantrithuc.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=4401"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}